Re: Data Sheets


May 17, 2003

 


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#1182 May 17, 2003

I'm looking at the 16f84 data sheet page 8. Maybe I'm not seeing

something, but it seems to me to have some errors.



Shouldn't the fsr register have an 8 bit bus interfacing to the addr

mux? It was my undertsanding that the RPO bit doesn't require

management when using the FSR because the bus is eight bits wide.

Shouldn't the bus from the addr reg to RAM also have eight bits?



Shouldn't the instruction reg have a seven bit bus to the

addr mux. I thought one could access 128 locations of RAM

within an assembly instruction (even if 128 locations are not

physically implemented). The data sheet shows a five bit bus giving

32 possible locations. I believe the bus should be 7 bits with RPO

making up the eighth bit.



I'm interested to know if others think it is an error and if not,

why?



All the best,



Tim



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#1185 May 18, 2003

I think you are correct about the Direct Address input to the MUX

being 7 bits wide. From pg 55 we can see 7 bits encoded in the

instruction.



From pg 19 we can also see that the MUX is indeed 7 bits wide and can

assume that on pg 8 the bank select bits are just not shown. Note

how bit 7 of FSR is concatenated with IRP to form the 2 bit bank

select with 7 bits of offset via the MUX.



In the end there is a 9 bit address: 2 bits of bank select and 7 bits

of offset from the MUX.



This is made much more obvious in the 16F877 datasheet.



--- In piclist@yahoogroups.com, "tjroland2002" troland@t...> wrote:

> I'm looking at the 16f84 data sheet page 8. Maybe I'm not seeing

> something, but it seems to me to have some errors.

>

> Shouldn't the fsr register have an 8 bit bus interfacing to the

addr

> mux? It was my undertsanding that the RPO bit doesn't require

> management when using the FSR because the bus is eight bits wide.

> Shouldn't the bus from the addr reg to RAM also have eight bits?

>

> Shouldn't the instruction reg have a seven bit bus to the

> addr mux. I thought one could access 128 locations of RAM

> within an assembly instruction (even if 128 locations are not

> physically implemented). The data sheet shows a five bit bus giving

> 32 possible locations. I believe the bus should be 7 bits with RPO

> making up the eighth bit.

>

> I'm interested to know if others think it is an error and if not,

> why?

>

> All the best,

>

> Tim


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